Conference paper

A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5th-order ΔΣ loop

This paper presents a 5th-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5th-order filter having a 2nd-order analog and a 3rd-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front end is programmable. The ASIC developed comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit Flash ADC. The latter drives a 3rd-order digital filter, which can be configured for different sensor parameters in order to ensure overall loop stability and optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300Hz bandwidth.


    STI IEL ELab., EPFL, Lausanne, Switzerland IME, FHNW, Windisch, Switzerland Colibrys SA, Neuchâtel, Switzerland

    Export Date: 19 January 2010

    Source: Scopus

    Art. No.: 5326033

    References: Condemine, C., A 0.8mA 50Hz 15b SNDR ΔΣ Closed-Loop 10g Accelerometer Using an 8th-order Digital Compensator (2005) ISSCC Dig. Tech. Papers, pp. 248-249. , Feb; Amini, B.V., Abdolvand, R., Ayazi, F., A 4.5mW Closed-Loop ΔΣ Micro-Gravity CMOS-SOI Accelerometer (2006) ISSCC Dig. Tech. Papers, pp. 1001-1002. , Feb; Wu, J., Fedder, G.K., Carley, L.R., A Low-Noise Low-Offset Chopper-Stabilized Capacitive-Readout Amplifier for CMOS MEMS Accelerometers (2002) ISSCC Dig. Tech. Papers, 478, pp. 428-429. , Feb; Wu, J., Fedder, G.K., Carley, L.R., A Low-Noise Low-Offset Capacitive Sensing Amplifier for a 50-μg/√Hz Monolithic CMOS MEMS Accelerometer (2004) IEEE J. Solid-State Circuits, 39, pp. 722-730. , May


    Record created on 2010-10-21, modified on 2016-08-08


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