Substrate current modeling for high-voltage smart power BCD technology
This paper presents a compact- and a macro-model for estimating and simulating the perturbations induced in the substrate by high-voltage transistors switching inductive loads. On one hand, it allows the designer to predict the amount of switching noise generated by a particular topology. On the other hand, it enables a wise choice of the positioning of sensitive low-voltage circuits around the noisy devices, as well as the choice of appropriate shielding structures. The models proposed are validated by measurements on a prototype circuit at 25°C. © 2008 IEEE.
WOS:000262463700036
2008
141
144
Laboratoire d'Electronique Générale (LEG), Ecole Polytechnique Fédérale de Lausanne (EPFL), CH-1015 Lausanne, Cited By (since 1996): 2, Export Date: 19 January 2010, Source: Scopus, Art. No.: 4606341, References: Murari, B., Bertotti, F., Vignola, G.A., (2002) Smart power ICs: Technologies and applications, , 2nd Edition, Springer, Berlin; Clement, F.J.R., Zysman, E., Kayal, M., Declercq, M., LAYIN: Toward a global solution for parasitic coupling modeling and visualization (1994) Custom Integrated Circuits Conference, pp. 537-540; Mitra, S., Rutenbar, R.A., Carley, L.R., Allstot, D.J., A methodology for rapid estimation of substrate-coupled switching noise (1995) Custom Integrated Circuits Conference, pp. 129-132; Schenkel, M., Pfàffli, P., Mettler, S., Reiner, W., Wilkening, W., Aemmer, D., Fichtner, W., Measurements and 3D Simulations of Full-Chip Potential Distribution at Parasitic Substrate Current Injection (2000) Solid-State Device Research Conference, pp. 600-603; Kayal, M., Saez, R.L., Pastre, M., The Reduction of switching noise using CMOS current steering logic (2003) Substrate Noise Coupling in Mixed-Signal ASICs, pp. 223-228. , Kluwer
REVIEWED
EPFL
| Event name | Event place | Event date |
Montreal, QC, Canada | June 22-25, 2008 | |