Standard static CMOS logic is responding to the requirement of high frequency and low power of digital systems. However, the digital switching noise generated by this logic is not suited for the design of performance mixed-signal integrated systems. In mixed-signal application the analog functionality can be affected by this digital switching noise and therefore resolution is degraded. The Current Steering Logic (CSL) is one of the well-known techniques capable of decreasing the switching noise [1,2]. Despite its static power consumption, the CSL is considered as a promising approach to achieve a good functionality in some mixed-signal application. In this paper a new automated design tool for deep submicron CSL library design is presented. This tool uses an iterative algorithm where EKV-MOSFET model [:3] is implemented to provide a good trade-off between power and speed.