Capacitorless 1T DRAM sensing scheme with automatic reference generation

To perform a current sensing in capacitorless 1-transistor (IT) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to-analog converter and a successive approximations algorithm. By setting the reference just below the current of the data state "1" the data retention time in the holding mode is maximized. The proposed scheme is evaluated in a 2-kb test chip implemented in a 1-mu m partially depleted (PD) SOI process. The measured retention time under holding conditions is higher than 1 s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip measures an access time of 25 ns with a read cycle time of 70 us.

Published in:
Ieee Journal of Solid-State Circuits, 41, 6, 1463-1470
Times Cited: 2

 Record created 2010-10-21, last modified 2018-03-17

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