In organic thin-film transistors (OTFTs), the conducting channel is located near the interface between the organic semiconductor and the dielectric; this interface is crucial for transistor performance. The goal of this thesis is to study the effect of this interface, especially when it is modified either by surface treatments or self-assembled monolayers. For this purpose, OTFTs based on pentacene and doped silicon wafer gate electrode and gold top contacts are fabricated. The dielectric is either silicon oxide (SiO2) or polyimide (PI). The dielectric surface affects both the growth of the pentacene film on the top of it and the electric performance of the transistor. The pentacene film morphology is studied on treated and untreated SiO2 and PI surfaces by AFM and water contact angle measurements. Depending on the nature of the dielectric surface, traps or charge transfer centers are introduced which then affect the performance of the transistor. The transistor performance is determined by measuring the drain current as it is dependent upon the drain and gate voltage. The contributions of the channel and the contacts are separated by 4-probe measurements (at floating and non-floating gate). The transistors with untreated dielectrics are first characterized. The dependence on the channel length, the thickness and the morphology of the pentacene film is studied. The short channels (2 – 20 µm) are patterned by stencil masks; the long channels (100 – 600 µm) by steel masks. The results show that the transistors with a channel length of 20 µm and smaller are limited by the contacts, while the transistors with a channel length between 100 and 600 µm are dominated by the channel, and thus the traps and residual carriers in the channel. The pentacene film morphology has more influence on the contact resistance than on the channel behavior. To study the effect of the interface modifications, the transistor behavior should be dominated by the channel and the contact effects minimized; hence, long-channel transistors are used. The dielectric surfaces are treated by plasma or pH solutions prior to the pentacene deposition resulting in a variety of defects. The defects are distinguished by those which lead to a change in the film growth and those which affect the electric performance by introducing traps or charge transfer centers. To overcome the influence of the dielectric surface, the oxide dielectric is passivated by a self-assembled monolayer (SAM). The neutral SAM acts as a spacer between the dielectric and the pentacene film and thus enhances the transistor performance. The polar SAMs also introduce a dipole moment. A series of molecules with a similar length, but different end groups, are used to investigate the effect of the dipole moment. The main result of this study is that the nature and the quality of the gate and the contact interfaces are often more important for the performance of the transistors than the thin film morphology.