Scalable Instruction Set Simulator for Thousand-core Architectures Running on GPGPUs


Published in:
Proceedings of the 2010 International Conference on High Performance Computing and Simulation (HPCS 2010), 459-466
Presented at:
Workshop on Exploitation of Hardware Accelerators (WEHA 2010), Caen, France, June 28- July 2, 2010
Year:
2010
Publisher:
New Jersey, USA, IEEE Press
ISBN:
978-1-4244-6828-7
Keywords:
Laboratories:




 Record created 2010-07-12, last modified 2018-03-17

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