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conference paper
A Family of Very Low-power Analog Building Blocks Based on CMOS Translinear Loops
1997
Proceedings of the 2nd IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design
Type
conference paper
Authors
Publication date
1997
Published in
Proceedings of the 2nd IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design
Start page
73
End page
78
Peer reviewed
REVIEWED
EPFL units
Available on Infoscience
June 24, 2010
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