Double-gate pentacene thin-film transistor with improved control in sub-threshold region

In this work double-gate pentacene TFT architecture is proposed and experimentally investigated. The devices are fabricated on a polyimide substrate based on a process that combines three levels of stencil lithography with standard photolithography. Similarly to the operation of a conventional double-gate silicon FET, the top-gate bias modulates the threshold voltage of the bottom-gate transistor and significantly improves the transistor sub-threshold swing and leakage current. Moreover, the double gate TFT shows good promise for the enhancement of I-ON/I-OFF, especially by the control of I-OFF in devices with poor top interfaces. (C) 2010 Elsevier Ltd. All rights reserved.


Published in:
Solid-State Electronics, 54, 9, 1003-1009
Year:
2010
Publisher:
Elsevier
ISSN:
0038-1101
Keywords:
Laboratories:




 Record created 2010-05-04, last modified 2018-03-18

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