Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

The down-scaling of conventional MOSFETs has led to an impending power crisis, in which static power consumption is becoming too high. In order to improve the energy-efficiency of electronic circuits, small swing switches are interesting candidates to replace or complement the MOSFETs used today. Tunnel FETs, which are gated p-i-n diodes whose on-current arises from band-to-band tunneling, are attractive new devices for low-power applications due to their low off-current and their potential for a small subthreshold swing. The numerical simulations presented in this thesis have been carried out using a non-local band-to-band tunneling model in Silvaco Atlas. Numerical simulations based on correct underlying models are important for emerging devices, since they can provide insights about optimization before fabrication is carried out, can aid the understanding of device physics through 1D and 2D cross sections, and can be the basis for the formation of an accurate compact model. In general, only CMOS-compatible materials and structures have been used in the Tunnel FET designs presented here. One goal of this thesis was to stay within the framework of what is possible in standard industrial nanoelectronics cleanrooms today, without requiring processes whose mastery lies many years in the future. For this reason, the focus of this thesis is on all-silicon devices, and heterostructures that incorporate other materials are only mentioned. In chapter three, the optimization of the static characteristics of a Tunnel FET is carried out, looking at gate structure (single or double), doping levels of each device region, gate dielectric permittivity, and silicon body thickness. A study of the reduction of the band gap at the tunnel junction is also presented, showing the resulting improvement in on-current and subthreshold swing. Chapter four introduces a new method for threshold voltage extraction in Tunnel FETs. This method has one key advantage over the commonly-used constant current threshold voltage extraction technique: it has a physical meaning. The transconductance method, which has already been used for conventional MOSFETs, pinpoints the Tunnel FET voltage at which the transition from strong control to weak control of the tunneling energy barrier width, and therefore the on-current, takes place. This is analogous to the threshold voltage in a conventional MOSFET which marks the transition from weak inversion to strong inversion at φs=2φF. It is found that Tunnel FETs have two threshold voltages, one in relation to the gate voltage, and the second in relation to the drain voltage, and each depends on the voltage applied at the opposite terminal. A length scaling study is carried out in chapter five, demonstrating the scaling limits of Tunnel FETs at gate lengths on the order of 10-20 nm, due to p-i-n diode leakage current that degrades the off-current. Tunnel FETs designed to have better electrostatic control of the tunnel junction by the gate can scale further before they hit this diode leakage limit at some small gate length. Chapter six presents an additive booster strategy for Tunnel FET optimization, and then uses the resulting optimized device as the basis of a parameter variation study. Here, one parameter is varied at a time, and the effects on the important characteristics (subthreshold swing, threshold voltage, and on-current) are evaluated. The parameters requiring the most control during fabrication are identified. Since Tunnel FETs are emerging devices, the most important future work will be to fabricate fully-optimized n- and p-type devices, and to develop accurate compact models for their incorporation into circuits.

Ionescu, Mihai Adrian
Riess, Walter
Lausanne, EPFL
Other identifiers:
urn: urn:nbn:ch:bel-epfl-thesis4729-5

 Record created 2010-04-29, last modified 2018-01-28

Rate this document:

Rate this document:
(Not yet reviewed)