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conference paper
A 16-bit, 150-μW, 1-kS/s ADC with hybrid incremental and cyclic conversion scheme
2009
Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS 2009)
This paper presents the design, realization and characterization of a new hybrid A/D converter based on a combined incremental and cyclic conversion. The proposed implementation offers a configurable resolution, and permits to share the same hardware for the two conversion principles, leading to a compact circuit with only one active element. Integrated into a 0.18-μm CMOS process technology, the ADC features a DNL of -0.8/+1.6 LSB and an INL of -1.2/+1.8 LSB. It provides a 1 kHz sampling frequency while dissipating 150 μW under 1.65 V of voltage supply.
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Name
[Rossi09]ICECS-2009-Rossi-Tanner-Final.pdf
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restricted
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1.24 MB
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Adobe PDF
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