Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

The role of Field-Programmable Gate Arrays (FPGAs) in System-on-Chip (SoC) design considerably increased in the last few years. Their established importance is due to the large amount of hardware resources they offer, as well as to their increasing performance, and furthermore to the support for reconfigurability. Even though FPGAs seem to have reached their maturity, there is still a lack of Computer-Aided Design (CAD) tools able to deal with dynamic reconguration. Existing algorithms aim at optimizing the performance of a set of applications, basing the computation on classic metrics (such as communication overhead), while reconfiguration-related issues are not taken into consideration. This work proposes a design methodology to map several applications on the FPGA area at run-time. Starting from a basic solution found at design-time for the initial set of applications, the proposed algorithm makes it possible to map a new application (not known at design-time), both minimizing the number of synthesis processes and optimizing the on-chip performance of the new application. Experimental results show that the proposed approach is able to achieve up to a 18% reduction in the number of reconfigurations with respect to an off-line static-mapping approach, while generally preserving the performance of the executed applications on the FPGA.


Published in:
Proceedings of the IEEE 2010 International Symposium on Circuits and Systems (ISCAS 2010), 1, 1, 3329-3332
Presented at:
IEEE 2010 International Symposium on Circuits and Systems (ISCAS), Paris, France, May 30 - June 2, 2010
Year:
2010
Publisher:
New York, IEEE Press
ISBN:
978-1-4244-5309-2
Keywords:
Laboratories:




 Record created 2010-03-25, last modified 2018-03-17

n/a:
Download fulltext
PDF

Rate this document:

Rate this document:
1
2
3
 
(Not yet reviewed)