A (256x256) Pixel 76.7mW CMOS Imager/ Compressor Based on Real-Time In-Pixel Compressive Sensing

A CMOS imager is presented which has the abil- ity to perform localized compressive sensing on-chip. In-pixel convolutions of the sensed image with measurement matrices are computed in real time, and a proposed programmable two- dimensional scrambling technique guarantees the randomness of the coefficients used in successive observation. A power and area- efficient implementation architecture is presented making use of a single ADC. A 256×256 imager has been developed as a test vehicle in a 0.18μm CIS technology. Using an 11-bit ADC, a SNR of 18.6dB with a compression factor of 3.3 is achieved after reconstruction. The total power consumption of the imager is simulated at 76.7mW from a 1.8V supply voltage.

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Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, May 30 - June 2, 2010
IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

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 Record created 2010-02-12, last modified 2020-07-30

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