Fabrication and Characterization of Gate-All-Around Silicon Nanowires on Bulk Silicon

This paper reports on the top-down fabrication and electrical performance of silicon nanowire (SiNW) gate-all-around (GAA) n-type and p-type MOSFET devices integrated on bulk silicon using a local-silicon-on-insulator (SOI) process. The proposed local-SOI fabrication provides various nanowire cross sections: Omega-like, pentagonal, triangular, and circular, all controlled by isotropic etching using nitride spacers and silicon sacrificial oxidation. The reported top-down SiNW fabrication offers excellent control of wire doping and placement, as well as ohmic source and drain contacts. A particular feature of the process is the buildup of a tensile strain in all suspended nanowires, attaining values of few percents, reflected in stress values higher than 2-3 GPa. A very high yield (&gt;90%) is obtained in terms of functionality of long-channel SiNW GAA mosfet. Device characteristics are reported from cryogenic temperature (<i>T</i> = 5 K) up to 150 <sup>deg</sup>C, and promising characteristics in terms of low-field electron mobility, threshold voltage control, and subthreshold slope are demonstrated. Low field mobility for electrons up to 850 cm<sup>2</sup> /Vmiddots is reported at room temperature in suspended devices with triangular cross sections; this mobility enhancement is explained by the process-induced tensile strain. In short, suspended SiNW GAA with small triangular cross sections, a single-electron transistor (SET) operation regime is highlighted at <i>T</i> = 5 K. This is attributed to a combined effect of strain and corner conduction in triangular channel cross sections, suggesting the possibility to hybridize CMOS and SET functions by a unique nanowire fabrication platform.

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Nanotechnology, IEEE Transactions on, 7, 6, 733-744

 Record created 2010-01-08, last modified 2018-09-13

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