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  4. Fault-Tolerance and Reliability of Post-CMOS Systems: a Circuit Perspective
 
conference paper

Fault-Tolerance and Reliability of Post-CMOS Systems: a Circuit Perspective

Stanisavljevic, Milos  
•
Schmid, Alexandre  
•
Leblebici, Yusuf  
2009
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

The reliability of systems made of unreliable nanoelectronic devices is discussed in this paper. Massive defect density which may affect future fabrication technologies calls for novel solutions, where spatial redundancy and the voting scheme play a significant role. The averaging and thresholding voting mechanism that was used in CMOS technologies is presented in the context of nanodevices, based on SET circuits. Theoretical developments supported by numerical simulations show that the presented voter and circuit architecture are also applicable in nanoelectronic design, and are superior to classical voters.

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Type
conference paper
DOI
10.1109/ISPACS.2009.5383810
Web of Science ID

WOS:000289915800108

Author(s)
Stanisavljevic, Milos  
Schmid, Alexandre  
Leblebici, Yusuf  
Date Issued

2009

Publisher

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

Published in
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
Start page

433

End page

436

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSM  
Event nameEvent placeEvent date
International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

Kanazawa, Japan

December 6-8, 2009

Available on Infoscience
November 19, 2009
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/44323
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