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conference paper
Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays
2009
Proceedings of the 39th European Solid-State Device Research Conference (ESSDERC)
We describe the fabrication of vertically stacked Silicon Nanowire Field Effect Transistors (SiNWFETs) in Gate-All Around (GAA) configuration. Stacks with the number of channels ranging from 1 to 12 have been successfully produced by means of a micrometer scale lithography and conventional fabrication techniques. It is shown that demonstrator Schottky Barrier (SB) devices fabricated with Cr/NiCr contacts present good subthreshold slope (70mV/dec), ION/IOFF ratio $>= 10^4$ and reproducible ambipolar behavior.
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05331516.pdf
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openaccess
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1.75 MB
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Adobe PDF
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