Power Distribution Paths for 3-D IC

Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (TSVs) in most of the manufacturing techniques for three-dimensional (3-D) circuits. As shown in this paper, these vertical interconnects provide additional low impedance paths for distributing power and ground within a 3-D circuit. These paths, however, have not been considered in the design process of 3-D power and ground distribution networks. By exploiting these additional paths, the IR drop within each plane is reduced. Alternatively, the routing congestion caused by the TSVs can be decreased by removing stacks of metal vias that are used within a power distribution network. Additionally, the required decoupling capacitance for a circuit can be reduced, resulting in significant savings in area. Case studies of power grids demonstrate a significant reduction of 22% in the number of intraplane vias. Alternatively, a 25% decrease in the decoupling capacitance can be achieved.

Published in:
Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI 2009), 263-268
Presented at:
ACM Great Lakes Symposium on VLSI (GLSVLSI 2009), Boston, Massachusetts, USA, May 10-12, 2009
ACM Order Department, P.O. Box 64145, Baltimore, MD 21264 USA

 Record created 2009-10-15, last modified 2019-03-16

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