Clock and Power Distribution Networks for 3-D ICs

Global interconnect design for threedimensional integrated circuits is a crucial task. Despitethe importance of this task, limited results related to global issues have been presented. Challenges in reliably distributing power, ground, and the clock signal within a multi-plane integrated system are discussed in this paper. The design of two 3-D test circuits addressing these issues is described. Candidate 3-D topologies for both power and clock distribution networks are also presented. Design implications due to the different design approaches are discussed. Experimental and simulation results of the 3-D clock and power distribution architectures, respectively, are provided. Both of the test circuits are fabricated by the 3-D fabrication process developed at MIT Lincoln Laboratories (MITLL). The design of the clock and power distribution networks is discussed

Published in:
Proceedings of the IEEE Conference on Design, Automation, and Test in Europe (DATE 2009)
Presented at:
IEEE Conference on Design, Automation, and Test in Europe (DATE 2009), Nice, France, April 20-24, 2009

 Record created 2009-10-15, last modified 2019-03-16

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