Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique

Silicon nanowires are a promising solution to address the increasing challenges of fabrication and design at the future nodes of the Complementary Metal-Oxide-Semiconductor (CMOS) Technology roadmap. Despite the attractive opportunity that offers their organization onto regular crossbars, the problem of designing the nanowire decoder is still challenging and highly dependent on the nanowire fabrication technology. In this paper, we introduce a novel design style and encoding scheme for decoding nanowires fabricated with the Multi-Spacer-Patterning Technique (MSPT); and we present a method based on Gray codes that reduces the fabrication cost and improves the decoder reliability. We show that by arranging the code in a Gray code fashion, we decrease the fabrication complexity by 17% and the variability by 18% on average. By optimizing the decoder parameters, the simulations showed an improvement of the crossbar yield by 40% and a reduction of the effective bit area by 51% to 169 nm2.

Published in:
Proceedings of the 46th Design Automation Conference (DAC)
Presented at:
46th Design Automation Conference (DAC), San Francisco, California, USA, July 26-31, 2009
IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, NJ 08855-1331 Usa

 Record created 2009-10-12, last modified 2019-03-16

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