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  4. Low voltage Ferroelectric FET with sub-100nm copolymer P(VDF-TrFE) gate dielectric for non-volatile 1T memory
 
conference paper

Low voltage Ferroelectric FET with sub-100nm copolymer P(VDF-TrFE) gate dielectric for non-volatile 1T memory

Salvatore, G. A.  
•
Bouvet, D.  
•
Stolitchnov, I.  
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2008
Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European

A polymer based Ferroelectric gate FET at 1T non-volatile memory on bulk silicon is demonstrated. Spin-coated 40 nm and 100 nm P(VDF-TrFE) (70%-30%) ultra-thin films have been integrated onto 10 nm SiO₂ layer as gate dielectric into a conventional silicon n-MOSFETs. A 1T non-volatile memory cell with an operating voltage as low as 6 V, for the thinnest (40 nm) gate ferroelectric copolymer dielectric, is demonstrated for the first time. The reported Fe-FET devices have Ion/Ioff ranging from $10^5$ to $10^6$ and retention time up to few days. Experiments show reliable memory operation up to $10^5$ cycles and programming time in the order of ms.

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Type
conference paper
DOI
10.1109/ESSDERC.2008.4681724
Web of Science ID

WOS:000262973300037

Author(s)
Salvatore, G. A.  
Bouvet, D.  
Stolitchnov, I.  
Setter, N.  
Ionescu, A. M.  
Date Issued

2008

Published in
Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European
Start page

162

End page

165

Subjects

MOSFET

•

conducting polymers

•

ferroelectric devices

•

polymer blends

•

polymer films

•

semiconductor storage

•

copolymer gate dielectric

•

low voltage ferroelectric FET

•

nonvolatile memory

•

spin coating

•

ultrathin films

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
LC  
Available on Infoscience
July 15, 2009
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/41348
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