Low voltage Ferroelectric FET with sub-100nm copolymer P(VDF-TrFE) gate dielectric for non-volatile 1T memory

A polymer based Ferroelectric gate FET at 1T non-volatile memory on bulk silicon is demonstrated. Spin-coated 40 nm and 100 nm P(VDF-TrFE) (70%-30%) ultra-thin films have been integrated onto 10 nm SiO₂ layer as gate dielectric into a conventional silicon n-MOSFETs. A 1T non-volatile memory cell with an operating voltage as low as 6 V, for the thinnest (40 nm) gate ferroelectric copolymer dielectric, is demonstrated for the first time. The reported Fe-FET devices have Ion/Ioff ranging from $10^5$ to $10^6$ and retention time up to few days. Experiments show reliable memory operation up to $10^5$ cycles and programming time in the order of ms.

Published in:
Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European, 162-165

 Record created 2009-07-15, last modified 2018-09-13

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