Pentacene - SiO2 interface: Role of the environment prior to pentacene deposition and its impact on TFT DC characteristics

In this paper we report on the effect of the environment on the SiO₂/pentacene interface. Two batches of bottom-contact pentacene thin-film transistors have been fabricated with a 100 nm thick SiO₂ as dielectric. Considerable shifts of the threshold voltages have been observed for the TFTs whose dielectric surface has been exposed to air for long periods of storage before depositing the pentacene layer. Based on reports from other research groups in the field, we consider that long exposure of the SiO₂ to air may have the same effect on the SiO₂-pentace interface as short but more aggressive oxygen plasma treatment.


Published in:
None
Presented at:
26th International Conference on Microelectronics (MIEL 2008), Nis, Serbia, May 11-14, 2008
Year:
2008
Publisher:
IEEE
Keywords:
Laboratories:


Note: The status of this file is: Involved Laboratories Only


 Record created 2009-07-15, last modified 2018-09-13

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preprintCvetkovic_2008_MIEL - Download fulltextPDF
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