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research article
Low test application time resource binding for behavioral synthesis
Recent advances in process technology have led to a rapid increase in the density of integrated circuits (ICs). Increased density and the need to test for new types of defects in nanometer technologies have resulted in a tremendous increase in test application time (TAT). This article presents a test synthesis method to reduce test application time for testing the datapath of a design. The test application time is reduced by applying a test-time-aware resource sharing algorithm on a scheduled control data flow graph (CDFG) of a design.
Type
research article
Authors
Publication date
2007
Volume
12
Issue
2
Start page
16
Peer reviewed
REVIEWED
EPFL units
Available on Infoscience
May 23, 2009
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