Cacheable Interface Control Registers for High Speed Data Transfer
A device interface for communicating between a processor system and a separate device employs cacheable control registers, both to indicate the receipt of a message and to receive messages to be transmitted. The data structure of the cacheable control registers may be that of a queue, minimizing the need for routine handshaking signals to clear the queue after each message. Communication of queue pointers is minimized by the use of a shadow pointer relied on as long as adequate queue space exists and queue entry valid flags which are interpreted with alternate sense for each cycling through the queue.
26693334
Alternative title(s) : (en) Cacheable interface control registers for high speed data transfer
Patent number | Country code | Kind code | Date issued |
US5951657 | US | A | 1999-09-14 |