Predictor virtualization

Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these optimizations usually require large dedicated on-chip tables. Although technology advances offer an increased amount of on-chip resources, these resources are allocated to increase the size of on-chip conventional cache hierarchies. This work proposes Predictor Virtualization, a technique that uses the existing memory hierarchy to emulate large predictor tables. We demonstrate the benefits of this technique by virtualizing a state-of-the-art data prefetcher. Full-system, cycle-accurate simulations demonstrate that the virtualized prefetcher preserves the performance benefits of the original design, while reducing the on-chip storage dedicated to the predictor table from 60KB down to less than one kilobyte. Copyright © 2008 ACM.

Published in:
Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, 157-167
Presented at:
the 13th international conference on Architectural support for programming languages and operating systems (ASPLOS), Seattle, WA, March
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 Record created 2009-04-06, last modified 2020-10-25

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