Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery

Diminutive devices and high clock frequency of future microprocessor generations are causing increased concerns for transient soft failures in hardware, necessitating fault detection and recovery mechanisms even in commodity processors. In this paper, we propose a fault-tolerant extension for modern superscalar out-of-order datapath that can be supported by only modest additional hardware. In the proposed extensions, error-detection is achieved by verifying the redundant results of dynamically replicated threads of executions, while the error-recovery scheme employs the instruction-rewind mechanism to restart at a failed instruction. We study the performance impact of augmenting superscalar microarchitectures with this fault tolerance mechanism. An analytical performance model is used in conjunction with a performance simulator The simulation results of 11 SPEC95 and SPEC2000 benchmarks show that in the absence of faults, error detection causes a 2% to 45% reduction in throughput, which is in line with other proposed detection schemes. In the presence of transient faults, the fast error recovery scheme contributes very little additional slowdown

Published in:
Proceedings of the 34th Annual IEEE/ACM International Symposium on Microarchitecture, 214-224
Presented at:
34th Annual IEEE/ACM International Symposium on Microarchitecture, Austin, Texas, December 1-5, 2001

 Record created 2009-04-06, last modified 2019-12-05

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