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Latest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowires, etc.) have deployed bottom-up techniques that reach feature sizes well below 65nm, holding great promise for future large silicon-based integrated circuits. However, new nano-devices intrinsically have much higher failure rates than CMOS-based ones. Thus, new design methodologies must address the combination of devicelevel error-prone technologies with system integration constraints (low power, performance) to deliver competitive devices at the nanometer scale. In this paper we show that a very promising way to achieve nano-scale devices is combining imperfection-aware design techniques during fabrication with gate defect modeling at circuit level. Our results using this approach to define a Carbon Nanotube Field-Effect Transistor (CNFET)-based design flow for nanoscale logic circuits attain more than 3x energy-delay-product advantage compared to 65nm CMOS-based ones.