A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak) chip-level clock distribution is ensured by five-level balanced clock tree, implemented in low swing current-mode logic. The ADC block achieves a peak SFDR of 71.3 dB and 9.26 ENOB at 230 MS/s, with an input signal swing of 1.5Vpp. The measured peak SFDR at 200 MS/s is 78 dB, while the peak SNDR at 200 MS/s is 59.5 dB. The SFDR and SNDR performance exhibits very flat characteristics, maintaining higher than 53 dB SNDR at 230 MS/s and higher than 58 dB SNDR at 200 MS/s, from DC through Nyquist rate input frequencies.

Published in:
IEEE Asia-Pacific Conference on Circutis and Systems, 21-24
Presented at:
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Macao, China, November 30 - December 3
China, IEEE

 Record created 2009-01-15, last modified 2018-03-17

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