Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level

In current multimedia applications like 3D graphical processing or games, the run-time memory management support has to allow real-time memory de/allocation, retrieving and data processing. The implementations of these algorithms for embedded platforms require high speed, low power and large data storage capacity. Due to the large hardware/software co-design space, high-level implementation cost estimates are required to avoid expensive design modifications late in the implementation. In this paper, we present an approach designed to do that. Based on memory accesses, normalised memory usage1 and power estimates, the algorithm code is refined. Furthermore, optimal implementations for the dynamic data types involved can be selected with a considerable power contribution reduction.


Published in:
Proceedings of the 2003 Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2799, 1, 289-298
Presented at:
Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Turin, September 11-13, 2003
Year:
2003
Publisher:
Amsterdam, Springer
Keywords:
Laboratories:




 Record created 2009-01-11, last modified 2018-09-13

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