Custom Design of Multi-Level Dynamic Memory Management Subsystem for Embedded Systems

Modern embedded systems have to run new dynamic wireless network and multimedia applications. As a result, these systems must provide run-time memory management support to allow real-time memory de/allocation, retrieving and processing of data while very limited power supply is available. Thus, its implementation must be designed to combine high speed access, low power and large data storage capacity. This is only possible by an efficient use of the memory hierarchy available in the embedded systems. In this paper, we propose a new approach to design convenient dynamic memory management subsystems making profit of the multiple memory levels. It analyzes the logical phases involved in modern dynamic applications to effectively distribute the dynamically allocated data among the multi-level memory hierarchies present in embedded devices. We assess the effectiveness of the proposed approach for three representative real-life case studies of the new dynamic application domains (i.e., network and 3D rendering applications) ported to embedded systems. The results accomplished with our approach show a very significant reduction in energy consumption (up to 40%) over state-of-theart solutions for dynamic memory management on embedded systems with typical cache-main memory architectures while respecting the real-time requirements of these applications

Published in:
Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS'04), 1, 1, 170-175
Presented at:
IEEE Workshop on Signal Processing Systems (SIPS'04), Austin, October 12-16, 2004
New York, IEEE Press

 Record created 2009-01-11, last modified 2018-03-17

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