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conference paper
Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs
2005
Proceedings of the III IEEE International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘05)
In this paper we introduce a new hardware/software approach to reduce the energy of the shared register file in upcoming embedded architectures with several VLIW processors. This work includes a set of architectural extensions and special loop unrolling techniques for the compilers of MPSoC platforms. This complete hardware/software support enables reducing the energy consumed in the register file of MPSoC architectures up to a 60% without introducing performance penalties.
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IWIA05-ayalaAtienza.pdf
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openaccess
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Adobe PDF
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