Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs

In this paper we introduce a new hardware/software approach to reduce the energy of the shared register file in upcoming embedded architectures with several VLIW processors. This work includes a set of architectural extensions and special loop unrolling techniques for the compilers of MPSoC platforms. This complete hardware/software support enables reducing the energy consumed in the register file of MPSoC architectures up to a 60% without introducing performance penalties.


Published in:
Proceedings of the III IEEE International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘05), 1, 1, 65-71
Presented at:
III IEEE International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA ‘05), Oahu, Hawaii, USA, January 19-21, 2005
Year:
2005
Publisher:
New York, IEEE Press
ISSN:
1527-1366
Keywords:
Laboratories:




 Record created 2009-01-11, last modified 2018-03-17

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