Systematic Design Flow for Dynamic Data Management in Visual Texture Decoder of MPEG-4

There is a clear trend of future embedded systems in moving toward wireless, multimedia, multi-functional and ubiquitous applications. This emerges new challenges in the existing solutions on performance, power, flexibility and costs, calling for innovations in both architecture and design methodology. In this paper we propose a design flow consisting of three stages to handle dynamic data, allowing the designer to create highly customized dynamic memory managers, make them bank-aware and create a design-time schedule of the different tasks of the application. We evaluated the proposed flow using the Visual Texture Coding (VTC) application, mapping it on a dual processor embedded platform achieving 5.5% reduction in memory footprint and 10% gains in execution time.


Published in:
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'06), 2, 1, 4747-4750
Presented at:
IEEE International Symposium on Circuits and Systems (ISCAS'06), Kos, Greece, June 12-17, 2006
Year:
2006
Publisher:
New York, IEEE Circuits and Systems Society
Keywords:
Laboratories:




 Record created 2009-01-11, last modified 2018-09-13

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