Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime circuit delay, hence the leakage energy consumption depends on the supply voltage exponentially. By reducing the idle time of the circuit both the supply voltage that realizes minimum energy operation and the energy consumption can be reduced. This paper presents an in-depth comparison of synchronous and asynchronous techniques in the sub-threshold operating regime for their energy efficiency. First, transistor level accurate high level sub-threshold energy consumption model is developed for both techniques. Afterwards, using the model, energy consumption reduction due to the asynchronous operation is investigated analytically. Different architectural improvements such as pipelining and parallelism are considered. The model has also been applied to the benchmark circuits for comparing real world energy consumption values. From our analysis and simulations we have found out that asynchronous operation in the sub- threshold regime significantly lowers the supply voltage value that realizes the minimum energy operation and operating the digital circuits at a lower supply voltage value result in lower energy operation. Asynchronous operation resulted in energy consumption savings of up to 51% on the ISCAS85 benchmark circuits synthesized in a digital CMOS 0.18 m process.