Smart camera with embedded co-processor: a postal sorting application

This work describes an image acquisition and processing system based on a new co-processor architecture designed for CMOS sensor imaging. The platform permits to configure a wide variety of acquisition modes (random region acquisition, variable image size, multi-exposition image) as well as high-performance image pre-processing (filtering, de-noising, binarisation, pattern recognition). Furthermore, the acquisition is driven by an FPGA, as well as a processing stage followed by a Nexperia processor. The data transfer, from the FPGAs board to the Nexperia processor, can be pipelined to the co-processor to increase achievable throughput performances. The co-processor architecture has been designed so as to obtain a unit that can be configured on the fly, in terms of type and number of chained processing (up to 8 successive pre-defined pre-processing), during the image acquisition process that is dynamically defined by the application. Examples of acquisition and processing performances are reported and compared to classical image acquisition systems based on standard modular PC platforms. The experimental results show a considerable increase of the performances. For instance the reading of bar codes with applications to postal sorting on a PC platform is limited to about 15 images (letters) per second. The new platform beside resulting more compact and easily installable in hostile environments can successfully analyze up to 50 images/s.

Presented at:
Optical and Digital Image Processing , Strasbourg, France , April 7 2008
Strasbourg (France)

 Record created 2008-04-03, last modified 2018-01-28

External link:
Download fulltext
Rate this document:

Rate this document:
(Not yet reviewed)