Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage
Badel, Stéphane; Leblebici, Yusuf
2007

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Abstract

In this paper, we study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages.We show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly constant. We propose a negative bias strategy that enables the gates to operate at maximum speed with a reduced supply voltage, thus achieving a power saving of up to 35% at no cost for speed. Comparison with CMOS logic style are presented for three different technology nodes (0.25\u03bcm, 0.18\u03bcm and 0.13\u03bcm CMOS).

Details

Title Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage
Author(s) Badel, Stéphane ; Leblebici, Yusuf
Published in Proceedings of the IEEE International Symposium on Circuits and Systems
Pages 1871-1874
Conference IEEE International Symposium on Circuits and Systems, New Orleans, Louisiana, USA, May 27-30
Date 2007
Keywords
DOI https://doi.org/10.1109/ISCAS.2007.378280
Other identifier(s) View record in Web of Science
Laboratories LSM
Record Appears in Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > LSM - Microelectronic Systems Laboratory
Peer-reviewed publications
Conference Papers
Work produced at EPFL
Published
Record creation date 2007-12-13

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