Presentation / Talk

Stencil Lithography – Quick & Clean Surface Patterning at Mesoscopic Scales

Stencil lithography is a surface patterning technique that relies on the local physical vapor deposition of material through miniaturized shadow mask membranes. It is extremely useful for the formation of patterns, mainly thin structured metal films, in situations where lithography equipment is not available or when the surfaces don’t allow the chemical and thermal process steps typically involved in photolithography. Stencil lithography is scalable from mm to sub-100-nm sizes, which makes it very interesting as method for rapid-prototyping of nanostructures without the risk of contamination, and for laboratories without access to high-end nanolithography equipment. The major challenges in stencil lithography are following: i) low-cost fabrication of nanostencils, ii) optimized mechanical properties of thin membranes, iii) deposition of material on stencil membrane, iv) precise alignment of nanostencils, v) recycling of stencils. In collaboration with our project partners [1] we have recently progressed in several of the above mentioned challenges. Stencils fabrication can be based on a set of advanced silicon micro and nanomachining steps (including UV, DUV, EBL and FIB) and a combination of DRIE and wet etching. The mechanical stability of the ultra-thin low-stress silicon nitride membranes could be considerably improved by topographic reinforcement rims. Surface structures of metals (e.g. Al, Au, Bi, Cr, Ti, Cu) on various surfaces (e.g. Si, SiO2, SU-8, PDMS, PMMA, SAMs, freestanding SiN cantilevers, and curved surfaces) where systematically studied in terms of patterning accuracy. Thousands of sub-micrometer NEMS resonators were integrated in CMOS by stencil lithography and sacrificial etching. Variants of stencil methods include the local doping with ions, and local polymer etching using oxygen plasma. The talk will present the current state-of-the-art of nanostencil lithography, will highlight the strength of the method but will also discuss the current limits and challenges ahead to make it a truly reliable and scalable full-wafer nanofabrication method.


    • LMIS1-PRESENTATION-2007-040

    Record created on 2007-10-30, modified on 2016-08-08


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