Dry etching for the correction of gap-induced blurring and improved pattern resolution in nanostencil lithography
We present nanostencil lithography as a new and parallel nanopatterning technique for batch fabrication of micro/ nanoelectromechanical systems (MEMS/NEMS) with high throughput and resolution. We use nanostencil lithography for the purpose of integrating nanomechanical resonators into complementary metal-oxide semiconductor (CMOS) circuits. When patterning nonflat substrates, which is the case of CMOS wafers, the gap between the nanostencil membrane and the surface induces a pattern blurring that constitutes an intrinsic limitation to the maximum achievable resolution. In our case, the lateral blurring is on the order of 150 nm on each side. We present here a remedy to this limitation that is based on a corrective dry etching step that removes the excess material and which recovers the designed pattern dimensions. As a demonstration, we succeed in the patterning of an entire 100-mm-diam wafer with nanomechanical devices having lateral dimensions in the range of 200 nm.