Conference paper

Application of FPGA Emulation to SoC Floorplan and Packaging Exploration

New tendencies in the consumer electronics market present Multi-Processor Systems-On-Chip (MPSoCs) as a promising solution for meeting the processing demands of upcoming generations of user applications. MPSoCs are complex to design, as they must execute multiple applications real-time video processing, 3D games), while meeting additional design constraints (energy consumption, time-to-market). When an integrated system is built for a certain MPSoC, the definition of an appropriate floorplan is a very complex task for system integration designers. In fact, deciding a suitable placement of each block in the MPSoC architecture requires taking into account multiple constraints (e.g., power, energy, performance, etc) with values that are specific for each design. Recently, due to the increasing temperature in MPSoCs, thermal behavior has become another key factor to define the placement of each block of the design. In this context, we show how designers will benefit from applying our FPGA-based Emulation Framework to the MPSoC design cycle. Starting with a set of constrains (performance, latency...) and the HW elements of the system, with the help of our exploration tool, the thermal behaviour of different floorplan alternatives can be profiled at an early stage of the development cycle. It will also guide the designer in selecting the right packaging solution for the final chip, minimizing the cost without compromising the chip reliability. Our platform enables thermal monitorization of the final (real) applications over the different architectures, at speeds very close to real time, as opposed to SW simulators.


    • EPFL-CONF-110173

    Record created on 2007-08-15, modified on 2016-08-08

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