NoC Design and Implementation in 65 nm Technology

As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent. Networks-on-Chip (NoCs) have been proposed as a scalable solution to both physical design issues and increasing bandwidth demands. However, this claim has not been fully validated yet, since the design properties and tradeoffs of NoCs have not been studied in detail below the 100 nm threshold. This work is aimed at shedding light on the opportunities and challenges, both expected and unexpected, of NoC design in nanometer CMOS. We present fully working 65 nm NoC designs, a complete NoC synthesis flow and detailed scalability analysis.


Published in:
Proceedings of the First ACM/IEEE International Symposium on Networks-on-Chip (NOCS), IEEE Circuits and Systems Society, 273-282
Presented at:
First ACM/IEEE International Symposium on Networks-on-Chip (NOCS), Princeton, New Jersey, USA, May 7-9, 2007
Year:
2007
ISBN:
0-7695-2773-6
Laboratories:




 Record created 2007-08-15, last modified 2018-03-18

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