Hybrid continuous-discrete-time multi-bit delta-sigma A/D converters with auto-ranging algorithm
In wireless portable applications, a large part of the signal processing is performed in the digital domain. Digital circuits show many advantages. The power consumption and fabrication costs are low even for high levels of complexity. A well established and highly automated design flow allows one to benefit from the constant progress in CMOS technologies. Moreover, digital circuits offer robust and programmable signal processing means and need no external components. Hence, the trend in consumer electronics is to further reduce the part of analog signal processing in the receiver chain of wireless transceivers. Consequently, analog-to-digital converters with higher resolutions and bandwidths are constantly required. The ultimate goal is the direct digitization of radio frequency signals, where the conversion would be performed immediately after the front-end amplifier. ΔΣ-modulation-based converters have proved to be the most suitable to achieve the required performance. Switched-capacitor implementations have been widely used over the last two decades. However, recent publications and books have shown that continuous-time architectures can achieve the same performance with lower power consumption. Most designs found throughout the literature use a single- or few-bit internal quantizer with a high-order modulation. As a result, in order to achieve the resolutions and bandwidths required today, the sampling frequency must exceed 100MHz. This approach leads to non-negligible power consumption in the clock generation. Moreover, the presence of such fast squared signals is not suitable for a system-on-chip comprising radio frequency receivers. In this thesis we propose a low-power strategy relying on a large number of internal levels rather than on a high sampling frequency or modulation order. Besides, a hybrid continuous-discrete-time approach is used to take advantage of the accuracy of switched-capacitor circuits and the low power consumption of continuous-time implementation. The sensitivity to clock jitter brought about by the continuous-time stage is reduced by the use of a large number of levels. An auto-ranging algorithm is developed in this thesis to overcome the limitation of a large-size quantizer under low-voltage supply. Finally, the strategy is applied to a design example addressing typical specifications for a Bluetooth receiver with direct conversion.
Keywords: analog-to-digital conversion ; delta-sigma modulation ; multi-bit ; quantization noise ; hybrid architecture ; continuous-time ; discrete-time ; full clock-cycle sampling ; double-sampling ; digital calibration ; auto-ranging algorithm ; tracking quantizer ; dynamic element matching ; spectral shaping ; tree-structured encoder ; segmented DAC ; Bluetooth ; WCDMA ; GSM ; EDGE ; comparator ; CMOS technology ; fully-differential amplifier ; transconductance amplifier ; conversion analogique-numérique ; modulation delta-sigma ; multibit ; bruit de quantification ; architecture hybride ; temps continu ; temps discret ; échantillonnage sur deux demi périodes ; double échantillonnage ; calibration numérique ; algorithme d'ajustement automatique d'amplitude ; quantificateur ; appariement dynamique ; mise en forme spectrale ; encodeur à structure en arbre ; CAN segmenté ; Bluetooth ; WCDMA ; GSM ; EDGE ; comparateur ; technologie CMOS ; amplificateur différentiel symétrique ; amplificateur à transconductanceThèse École polytechnique fédérale de Lausanne EPFL, n° 3912 (2008)
Section de génie électrique et électronique
Faculté des sciences et techniques de l'ingénieur
Institut de microélectronique et microsystèmes
Laboratoire d'électronique générale 1
Record created on 2007-08-15, modified on 2016-08-08