Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we suggest a way to reduce the decoder size and keep it defect tolerant by using multiple threshold voltages (VT ), which is enabled by our underlying technology. We define two types of multi-valued decoders and we model the defect they undergo due to the VT variation. Multi-valued hot decoders appear more defect-tolerant than n-ary reflex- ive decoders and permit the addressing of more wires even under the most severe conditions. There are many combinations of decoder type and number of VT ’s yielding equal effective memory capacities. The optimal choice saves area up to 24%. We also show that the precision of the addressing voltages for decoders with unreliable VT ’s is a crucial parameter for the decoder design and permits a large saving in memory area.