Case Study of Fault-Tolerant Architectures for 90nm CMOS Cryptographic Cores

This paper presents a case study of different fault-tolerant architectures. The emphasis is on the silicon realization. A 128bit AES cryptographic core has been designed and fabricated as a main topology on which the fault-tolerant architectures have been applied. One of the fault-tolerant architectures is a novel four-layer architecture exhibiting a large immunity to permanent as well as random failures. Characteristics of the averaging/ thresholding layer are emphasized. Measurement results show advantage of four-layer architecture over triple modular redundancy in terms of reliability.


Published in:
3rd Conf. on Ph.D. Research in Microelectronics and Electronics
Presented at:
IEEE 3rd Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Bordeaux, France, July 2 - 5
Year:
2007
Publisher:
Bordeaux
Keywords:
Laboratories:


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 Record created 2007-06-26, last modified 2018-03-17

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