Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approach has been considered at low level of abstraction in order to implement robustness and faulttolerance into these devices. Moreover, fault tolerant properties of multi- layer feed-forward artificial neural networks have been demonstrated. Thus, we have implemented this concept at circuit-level, using spiking neurons. Using this approach, the NOT, NAND and NOR Boolean gates have been developed in the AMS 0.35 µm CMOS technology. A very straightforward mapping between the value of a neural weight and one physical parameter of the circuit has also been achieved. Furthermore, the logic gates have been simulated using SPICE corners analysis which emulates manufacturing variations which may cause circuit faults. Using this approach, it can be shown that fault-absorbing neural networks that operate as the desired function can be built.

Published in:
Proceedings of the 3rd Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Presented at:
IEEE 3rd Conference on Ph.D. Research in Microelectronics and Electronics, Bordeaux, France, July 2-5

 Record created 2007-06-13, last modified 2018-03-17

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