Realization of Multiple Valued Logic and Memory by Hybrid SETMOS Architecture
2005
Details
Title
Realization of Multiple Valued Logic and Memory by Hybrid SETMOS Architecture
Author(s)
Mahapatra, S. ; Ionescu, A. M.
Published in
IEEE Transactions on Nanotechnology
Volume
4
Issue
6
Pages
705-714
Date
2005
Other identifier(s)
DAR: 7622
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Laboratories
NANOLAB
Record Appears in
Scientific production and competences > STI - School of Engineering > IEM - Institut d'Electricité et de Microtechnique > NANOLAB - Nanoelectronic Devices Laboratory
Peer-reviewed publications
Work produced at EPFL
Journal Articles
Published
Peer-reviewed publications
Work produced at EPFL
Journal Articles
Published
Record creation date
2007-05-16