Improving the Fault Tolerance of Nanometric PLA Designs

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric laments such as Silicon NanoWires (SiNWs) and Carbon NanoTubes (CNTs). However, chips leveraging these nanoscale structures are expected to be affected by a large amount of manufacturing faults, way beyond what chip architects have learned to counter. In this paper, we show a design ow, based on software mapping algorithms, to improve the yield of nanometric Programmable Logic Arrays (PLAs). While further improvements to the manufacturing technology will be needed to make these devices fully usable, our ow can signi cantly shrink the gap between current and desired yield levels. Also, our approach does not need post-fabrication functional analysis and mapping, therefore dramatically cutting on veri cation costs. We check PLA yields by means of an accurate analyzer after Monte Carlo fault injection. We show that, compared to a baseline policy of wire replication, we achieve equal or better yields (8% over a set of designs) depending on the underlying defect assumptions.

Published in:
Proceedings of Design Automation and Test in Europe (DATE), 570-575
Presented at:
Design Automation and Test in Europe (DATE), Nice, France, April 16-20, 2007

 Record created 2007-04-26, last modified 2019-03-16

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