Conference paper

Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework

With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple complex real-time applications (e.g. video processing, or videogames), while meeting several additional design constraints (e.g. energy consumption or time-to-market). Thus, in order to explore all the possible HW-SW configurations in a MPSoC, simulation is not practical anymore due to the large overhead in time of cycle-accurate simulators, which is the desired level for the extraction of statistics. New methods to extract such fine-grained statistics in a faster way are needed. In this paper, we present a new FPGA-based emulation framework that allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level. Our experimients using this platform yield a speed-up of three orders of magnitud compared to cycle-accurate MPSoC simulators, while achieving the same level of accuracy as cycle-accurate MPSoC simulation frameworks.


    • EPFL-CONF-100054

    Record created on 2007-02-06, modified on 2017-05-12

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