Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leading to an impending power crisis in which static power consumption reaches unacceptably high levels. Indeed, due to the relation between supply voltage (VD D ) and power dissipation of modern circuit technologies, when the supply voltage has been reduced from 0.5V to 0.25V while preserving the same overdrive, the leakage power in a 45-nm bulk CMOS technology has been shown to increase by a factor 275 . The work in this thesis proposes two synergic, promising strategies to overcome such limitations. The first aims to accompany conventional CMOS devices toward their ultimate limits of miniaturization via the Gate-All-Around (GAA) architecture, while the second relies on a new emerging device, the Tunnel-FET, which is based on a different working principle that anticipates remarkable advantages in the context of low-supply voltage applications. In particular, these two solutions allow three different scenarios. The GAA is able to provide the same Ion of High Performance (HP) planar MOSFET with a remarkable Ioff reduction thanks to a subthreshold swing improvement down to ∼ 60mV/dec at room temperature, with respect to ∼ 100mV/dec and ∼ 120mV/dec of planar Si-FETs and III-V FETs respectively. Whereas in the context of moderate performance or subthreshold region operation, when compared to CMOS, Tunnel-FETs offer superior performance at same low-supply voltage (for VDD < 0.4V ), or significant power reduction at same performance (because of a VDD reduction enabled by the steep off-on transition). Via the presentation of basic electrostatic concepts of heteromaterial systems common to both MOSFET and Tunnel-FETs and the Short-Channel-Effects that are plaguing planar CMOS of the current generation, we show that the Gate-All-Around device proves to be a pivotal solution capable of addressing the limitations of the aforementioned currently-used transistors. In particular, we study peculiarities of multi-gate devices with polygonal cross sections (such as those fabricated in our lab), namely corner effects and local volume inversion, and propose a model for the device electrostatics by means of an approximate solution to the 3D Poisson’s equation. We then provide the setting for our second research contribution by introducing the interband tunneling. A Band-to-Band Tunneling (BTBT) model is implemented in a full-band Monte Carlo simulator, the results of which are presented and analyzed. An analytical compact model for reverse-biased diodes is also developed and implemented in Verilog-A SPICE circuit simulator. We show that this model, validated by means of finite element simulations and comparison with experimental data, successfully describes and models both direct and indirect BTBT in both homo- and hetero-junction devices. Our final research contribution provides a launch pad for future research via an in-depth study and analysis of the conventional Tunnel-FET: device electrostatics, charge carriers and Fermi-Dirac distribution dependence on terminal biases are related to device-current dependence and peculiar features of such transistors, such as poor driving capability of all-Silicon devices, superlinear onset of output characteristics and progressively-degraded subthreshold swing by increased source doping, are explained. We develop and propose improved device architectures that prove to be extremely promising with superior potential towards the end of vastly improved performance within the low supply voltage domain. We further provide a DC analytical model and we performe circuit analyses to project and extrapolate the potential performance of Tunnel-FET, with the objective of predicting the spectrum of applications where it proves to be superior than conventional CMOS.