A Low-Latency and High-Performance SCL Decoder with Frame-Interleaving
In this paper, we describe a frame-interleaving hardware architecture for a generalized node-based successive cancellation list (SCL) decoder. By efficiently reusing otherwise idle computational units, two independent frames can be decoded simultaneously, resulting in a significant throughput gain. Based on this new architecture, we also exploit graph ensembles to diversify the decoding, enhancing the error-correcting performance by 0.28 dB and reducing the worst-case latency for serial graph processing by over 32%. Implementation results show that the proposed SCL decoder with frame-interleaving architecture achieves a throughput of 7.15 Gbps and an area efficiency of 37.63 Gbps/mm2, which is 1.56× and 1.11× better than the state-of-the-art node-based SCL decoders.
2-s2.0-85198560700
University of Science and Technology of China
École Polytechnique Fédérale de Lausanne
École Polytechnique Fédérale de Lausanne
University of Science and Technology of China
Technische Universiteit Eindhoven
Southeast University
École Polytechnique Fédérale de Lausanne
2024
9798350330991
REVIEWED
EPFL
Event name | Event acronym | Event place | Event date |
Singapore, Singapore | 2024-05-19 - 2024-05-22 | ||