In this work, a detailed analysis of capacitance behavior of high voltage MOSFET (HV-MOS) e.g. LDMOS, VDMOS using device simulation is made. The impact of lateral non-uniform doping and drift region is separately analyzed. It is shown that the peaks in C-GD and C-GS capacitances of HV-MOS originate from lateral non-uniform doping. The drift region decreases the C-GD capacitance and increases the peaks in CGS and also gives rise to peaks in C-GG capacitances increasing with higher drain bias. It is also shown that trapped charge due to hot carrier degradation modulates (or introduce) the peaks amplitude and position in capacitances depending on hot hole or electron injection at drain or source side. This capacitance analysis will facilitate in optimization of the HV-MOS structure and also help in modeling of HV-MOS, including the hot carrier degradation.