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  4. Buffer optimization based on critical path analysis of a dataflow program design
 
conference paper

Buffer optimization based on critical path analysis of a dataflow program design

Casale Brunet, Simone  
•
Mattavelli, Marco  
•
Janneck, Jorn W.
2013
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
2013 IEEE International Symposium on Circuits and Systems (ISCAS)

The trade-off between throughput and memory constraints is a common design problem in embedded systems, and especially for streaming applications, where the memory in question usually occurs in the form of buffers for streams of data. This paper presents a methodology, based on the post-processing of dataflow execution traces, that enables designers to make principled choices in the design space for arbitrary streaming applications in a scalable manner. It significantly extends the class of applications over traditional compile-time-only techniques, and effectively enables designers to find a close-to-minimum solution for this NP-complete problem. A heuristic algorithm exploring different buffer size configurations lets designers choose appropriate alternatives and enables them to rapidly navigate the design space. Methodology and experimental results are demonstrated in an at-size scenario using a real-world MPEG-4 SP decoder.

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Type
conference paper
DOI
10.1109/ISCAS.2013.6572113
Author(s)
Casale Brunet, Simone  
Mattavelli, Marco  
Janneck, Jorn W.
Date Issued

2013

Publisher

IEEE

Published in
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
Start page

1384

End page

1387

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
SCI-STI-MM  
Event nameEvent placeEvent date
2013 IEEE International Symposium on Circuits and Systems (ISCAS)

Beijing, China

19-23 05 2013

Available on Infoscience
September 30, 2013
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/95040
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