Hardware Architecture for List Successive Cancellation Decoding of Polar Codes
This brief presents a hardware architecture and algorithmic improvements for list successive cancellation (SC) decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a blocklength of N = 1024 bits and list sizes L = 2, 4 using a UMC 90 nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mb/s at a frequency of 459 MHz.
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Balatsoukas-Stimming, A., Raymond, A. J., Gross, W. J., & Burg, A. (2014). Hardware Architecture for List Successive Cancellation Decoding of Polar Codes. IEEE Transactions on Circuits and Systems II: Express Briefs, 61(8), 609–613. https://doi.org/10.1109/Tcsii.2014.2327336
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WOS:000341575000013
2014
61
8
609
613
REVIEWED
EPFL