The output conductance and transconductance are key small-signal parameters that typically set the dc gain of amplifiers. Although the transconductance can be modelled simply and accurately, modeling the output conductance over a large range of bias and geometries is much more challenging. In advanced technologies the self-gain has shrunk dramatically, while the transit frequency has increased significantly. The de-signer can hence choose a transistor length longer than minimal achieving a higher dc gain while still meeting the frequency specifications. Now, how much longer than minimum should he choose? We will try to answer this question by proposing a simple output conductance model that is valid over a wide range of bias and geometries. The model is validated by simulations for a 28-nm FDSOI CMOS process.